标题：Design for Adaptability and Security of Integrated Circuits

报告人：李兵

报告时间：2018年10月20日 (周六) 9:00

报告地点：数计学院2号楼311

摘要：

At submicron manufacturing technology nodes, process variations affect circuit performance

significantly. This trend usually leads to a large timing margin to maintain yield. To combat this pessimism, post‐silicon clock tuning can be applied to improve yield by balancing timing budgets of critical paths in chips after manufacturing. In this talk, a method to determine the number and locations of clock tuning components is presented. For tuning chips after manufacturing, a post‐silicon test strategy is also introduced. Furthermore, the concept of balancing timing budgets between combinational paths across flip‐flop stages is generalized into a new design perspective, which also enables protection of circuit netlists from counterfeiting.

报告人简介：

Bing Li received the bachelor’s and master’s degrees in communication and information engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 2000 and 2003, respectively. He received the Dr.‐Ing. degree in electrical engineering from Technical University of Munich (TUM), Munich, Germany, in 2010, where he also finished his Habilitation in 2018. He is currently a researcher with the Chair of Electronic Design Automation, TUM. His research interests include high‐performance and lower‐power design of integrated circuits as well as computing systems with emerging technologies.